The present invention relates to a multi-bit match detection circuit provided in, for example, a cache memory, which detects if a multi-bit read signal read out from a memory cell matches a data signal, the object of comparison, with said read signal.
The following are known as the prior arts related to the present invention:
(Reference 1)IEEE International Solid-State Circuit Conference, (1996), Mizuno. H, et. al., "A 1V 100 MHz 10 mV Cache using Separated Bit-Line Memory Hierarchy and Domino Tag Comparators", pp. 152-153. PA0 (Reference 2)IEEE International Solid-State Circuit Conference, (1997), Osada. K, et. al., "A 2 ns Access, 285 MHz, Two-Port Cache Macro using Double Global Bit-Line Pairs, pp. 402-403.
A cache memory is a memory which has a specific memory area for temporarily storing data for current operation of a processor, which data is stored in a main storage. Thus, the cache memory can access for read/write operation faster than the main storage. For this reason, the cache memory is provided with a multi-bit match detection circuit, which is called a tag comparator, for the purpose of detecting whether of not a copy of an address of the main storage is applied by the processor to the memory area of the cache memory.
FIG. 2 is a block diagram of a tag comparator in the prior art provided in a cache memory described in Reference 1.
The tag comparator includes n sets of comparison units 10.sub.i (i=1 to n). Each comparison unit 10.sub.i is connected with bit line pair 1.sub.i, 2.sub.i of n sets of memory cells (not shown). From the bit line pair l.sub.i, 2.sub.i, complementary read signals Bi, /Bi (/ indicates "reverse") are output. Each comparison unit 10.sub.i is also connected with address line pair 3.sub.i, 4.sub.i. From the address line pair 3.sub.i, 4.sub.i, complementary tag address signals Ai, /Ai (/ indicates "reverse") are output.
Each comparison unit 10.sub.i is structured identically. For example, a comparator unit 10.sub.1 has P-channel MOS transistors (hereinafter referred to as "PMOS") 11 and 13 and PMOS 12 and 14, constituting an exclusive OR (hereinafter referred to as "EOR") circuit. The comparison unit 10.sub.1 further comprises an output line 15.sub.1 for outputting EOR of a read signal B1 and a tag address signal A1, and an output line 16.sub.1 for outputting NOT of said EOR (hereinafter referred to as "ENOR").
Each output lines 15.sub.i, 16.sub.i of the comparison units 10.sub.i are connected with amplifier units 20.sub.i. Each amplifier unit 20.sub.i is structured identically for amplifying a level of complementary signals output to the output lines 15.sub.i, 16.sub.i to a predetermined logic level. For example, the amplifier unit 20.sub.1 has PMOS 21, 22 constituting a flip-flop type sense amplifier, N-channel MOS transistor (hereinafter referred to as "NMOS") 23, 24, and NMOS 25 for controlling operation of the sense amplifier.
An enable signal EN is applied to a gate of the NMOS 25 of the first stage amplifier unit 20.sub.1, to start comparison operation. The amplifier 20.sub.1 is designed to start operation when the enable signal EN is at "H" level. The output line 16.sub.i of the i.sup.th stage amplifier unit 20.sub.i is connected with the gate of the NMOS 25 of the succeeding stage amplifier unit 20.sub.i+1, operation of which is controlled sequentially by an output signal of the preceding stage amplifier unit 20.sub.i. A match signal HIT is output from the output line 16.sub.n of the last stage amplifier unit 20.sub.n.
In addition, the tag comparator is provided with a decision unit 30 for deciding if every bit matches the corresponding bit of the object of comparison. The decision unit 30 comprises an output line 31 for outputting a mismatch signal MH at "L" level when any pair of the corresponding bits do not match each other, multiple NMOS 32.sub.i for pulling down the output line 31 to "L" level when mismatch bits are found, and a PMOS 33 for pulling up the output line 31 to "H" level before decision by means of a pre-charge signal PRC.
The output line 15.sub.i of the each amplifier unit 20.sub.i is connected to the gate of a corresponding NMOS 32.sub.i. The drain of each NMOS 32.sub.i is commonly connected with the output line 31, and the source of the same is connected to a ground potential GND.
The following operation is carried out in the above mentioned tag comparator.
First, the complementary tag address signals Ai, /Ai, which are the object of comparison, are applied to each address line pair 3.sub.i, 4.sub.i. Further, memory cells in which address data are stored are selected, and the complementary read signal Bi, /Bi read out from the n sets of memory cells are thereby output to the bit line pairs 1.sub.i, 2.sub.i, respectively. With this, the comparison results EOR, ENOR are output to the output lines 15.sub.i, 16.sub.i of each comparison unit 10.sub.i, signal level of which are lower than the predetermined logic level.
Next, in order to start comparison operation, the enable signal EN is switched to "H" level so that the first stage amplifier unit 20.sub.1 is ready for operation. With this, the level of the signals at the output lines 15.sub.1, 16.sub.1 of the comparison unit 10.sub.1 are amplified to the predetermined logic level. At this stage, if the read signal B1 and the tag address signal A1 match, the output line 15.sub.1 is turned to "L" level, whereas the output line 16.sub.1 is turned to "H" level.
When the output line 16.sub.1 turns "H" level so as to enable the succeeding stage amplifier unit 20.sub.2 to start operation, the level of the signals at the output lines 15.sub.2, 16.sub.2 of the comparison unit 10.sub.2 are amplified to the predetermined logic level. At this stage, if the read signal B2 and the tag address signal A2 do not match, the output line 15.sub.2 is turned to "H" level, whereas the output line 16.sub.2 is turned to "L" level. With this, the NMOS 32.sub.2 is turned on and the output line 31 is turned to "L" level so that the mismatch signal MH indicating that the tag address signal Ai and the read signal Bi do not match is output. The third and succeeding amplifier units 20.sub.3 to 20.sub.n do not start operation, because the output line 16.sub.2 is at "L" level.
In case that every corresponding bit of the tag address signal Ai and the read signal Bi match, the output line 16.sub.i is switched to "H" level sequentially by means of each amplifier unit 20.sub.i. The output line 16.sub.n of the last stage amplifier unit 20.sub.n outputs the match signal HIT.
As mentioned above, the tag comparator is structured to compare the tag address signal Ai with the read signal Bi bit by bit, and output the mismatch signal MH when the mismatch bits are found, stopping subsequent comparison. Therefore, it is made possible to reduce electric consumption comparing with the multi-bit match detection circuit in which all the bits are compared at a time.
However, the following problems are yet to be solved with regard to the multi-bit match detection circuit, i.e. the tag comparator in the prior art.
The multi-bit match detection circuit in the prior art does not compare all the bits at a time so that the amount of electric consumption can be lowered. However, in the multi-bit match detection circuit in the prior art, designing of the timing circuit is rather difficult, and time required to output comparison result always differs depending on various kinds of data. Moreover, the large number of bits requires long time to obtain the comparison result. This increases delay time. The object of the invention is to solve the above mentioned problem and to provide a novel and improved multi-bit match detection circuit wherein the amount of electric consumption can be reduced with scarcely increasing time for operation.